
module clk_divider #(
    parameter NUM_DIV = 8,
    parameter CNT_LEN = 4
)
(
    input clk,
    input rst_p,
    output reg clk_div
);    
    reg [CNT_LEN-1:0]cnt;
    
always @(posedge clk or posedge rst_p)
    if(rst_p) begin
        cnt     <= 0;
        clk_div    <= 1'b0;
    end
    else if(cnt < NUM_DIV / 2 - 1) begin
        cnt     <= cnt + 1'b1;
        clk_div    <= clk_div;
    end
    else begin
        cnt     <= 0;
        clk_div    <= ~clk_div;
    end
endmodule